Synopsys, Inc. has recently announced the certification of its AI-driven digital and analog design flows for Samsung Foundry’s SF2 process, marking a significant milestone in their collaboration. This achievement has been validated through multiple test chip tapeouts, showcasing the readiness of certified design flows for Samsung Foundry’s latest Gate-All-Around (GAA) process technology.
The digital and analog design flows are powered by Synopsys.ai™ EDA suite, offering enhanced power, performance, and area (PPA) optimization, ultimately accelerating analog design migration for Samsung Foundry customers. Through the utilization of Synopsys’ AI-driven design technology co-optimization solution, the SF2 process has been optimized to deliver superior results in PPA compared to traditional methods.
Furthermore, Synopsys and Samsung are continuing their collaboration by expanding their IP offerings for Samsung’s advanced process technologies. This includes the qualification of multi-die design reference flow and UCIe IP for the SF2 process, enabling accelerated 2.5D/3D heterogeneous integration. The partnership also extends to the development of Synopsys ASO.ai for accelerated analog design migration, catering to Samsung’s GAA processes.
Sanjay Bali, Vice President of Product Management and Strategy at Synopsys, emphasized the importance of ecosystem collaboration to support customers in achieving their design goals on Samsung’s SF2 and SF1.4 processes. Through the integration of AI-driven design flows and Synopsys IP, designers are provided with a reliable path to accelerate their time to market.
The collaboration with Samsung has resulted in remarkable performance gains, with 12% higher performance, 25% power reduction, and 5% area reduction achieved using Synopsys’ certified digital flow on the SF2 process. This validates the effectiveness of the partnership in addressing the industry’s demand for high-performance computing solutions.
Synopsys and Samsung are focusing on AI-driven EDA flows, leveraging tools like DSO.ai for productivity and PPA optimization and ASO.ai for analog design migration. The integration of new design techniques such as backside routing and nanosheet cell design enables customers to meet their power, performance, and area targets for Samsung’s SF2 process family.
In conclusion, Synopsys’ collaboration with Samsung continues to drive innovation in design techniques and methodology, facilitating the development of advanced GAA processes. With a broad portfolio of IP offerings and a focus on multi-die designs, Synopsys is committed to supporting chipmakers in reducing integration risk and accelerating time to silicon success across various industries.
For more information on Synopsys and its comprehensive silicon to systems design solutions, visit http://www.synopsys.com.
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